Conventional digital signal processors (DSPs) having an N-bit word length, only single precision division of a 2N-bit dividend by an N-bit divisor is supported by computational hardware for calculating one quotient bit during each instruction cycle. Typical word lengths used in most DSPs are 16, 24 and 32 bits. Generally, double precision division of a 4N-bit dividend by a 2N-bit divisor is not directly supported by computational hardware and therefore double precision division must be executed using software control techniques that are very slow because they require numerous computation cycles for the computation of each quotient bit.
The present invention provides direct hardware support for double precision division and enables double precision division to be executed at a rate of two instructions cycles for the computation of each quotient bit. In the preferred embodiment, to compute the 2N quotient result produced by dividing a 4N-bit dividend by a 2N-bit divisor requires just 4N+2 instruction cycles.